Electrically erasable and programmable read only memory (EEPROM) devices refer to a class of semiconductor memory devices in which the data stored therein may be erased and replaced with new data. In some conventional EEPROM devices, only one memory region can be erased or programmed at any given time. Flash memory devices are a type of EEPROM device that enable multiple memory regions to be erased or programmed simultaneously through one program operation. As such, flash memory devices can operate at higher speeds than other conventional EEPROM devices. However, after a specific number of erase operations, the reliability of flash memories and other EEPROM devices may deteriorate due to degradation of an insulating layer that covers the charge storage cells that store data in the devices.
Flash memory devices continue to store information after the power supply to the device is cut off. In addition, flash memory devices are relatively robust and resistant to damage when subjected to, for example, physical impact. Flash memory devices also exhibit relatively fast read access times. Because of these characteristics, flash memory devices are now widely employed for both code and data storage in, for example, battery powered electronic devices such as personal digital assistants, cellular telephones, digital cameras, portable gaming consoles, MP3 players and the like. Flash memory devices may also be used in home applications such as high-definition TVs, digital versatile disks (DVDs), routers, and global positioning systems (GPSs). Flash memory devices are generally classified into two groups, namely NOR flash memory devices and NAND flash memory devices based on the configuration of the logic gates included in the device.
Flash memory devices store information in arrays of transistors or “cells.” Typically, each cell in the device stores one bit of information. “Multi-level” flash memory devices are also known that can store more than one bit of information per cell by varying the charge amount stored in the floating gate of each cell.
Two important reliability characteristics of flash memory devices that have a floating gate structure are (1) the number of program (write)/erase cycles that the device can withstand without degradation (which is often referred to as the “endurance” of the device) and (2) the data-retention characteristics of the device. The endurance of the flash memory device is an important consideration because the repeated program/erase cycles (referred to herein as “cycling”) can subject oxide layers in the device to stresses that can cause failure such as, for example, breakdown of tunnel oxide layers in the device. The threshold voltage of a memory cell may be lowered due to such stresses, which may allow electrons to leak away from the floating gate of a programmed memory cell.
FIG. 1 is a graphical diagram illustrating the threshold voltage distributions for each state of a conventional flash memory device that stores multi-level data. In the example of FIG. 1, each memory cell of the flash memory device may be in one of four different states. As shown in FIG. 1, voltages Read1, Read2 and Read3 define the four states. In FIG. 1, the dashed lines illustrate a target threshold voltage distribution for each of the four states (i.e., the expected distribution of the threshold voltages for memory cells in each of the respective states). As illustrated by the above-described program/erase cycling effects can shift the threshold voltage distribution of programmed memory cells toward a lower voltage, as indicated by the threshold voltage distributions drawn with solid lines in FIG. 1. If this shift is large enough, some of the programmed memory cells may have a threshold voltage that is lower than a program verify voltage (e.g., voltages Read1, Read2 or Read3 in FIG. 1). When this occurs, read operations may fail due to the decrease in read margin that occurs as the threshold voltage of the memory cells is reduced.
The data-retention characteristics of the device are of potential concern because charges (electrons) stored in the device to represent a data bit can leak away from the floating gate through various mechanisms such as thermoionic emission and/or charge diffusion through defective interplay dielectrics, ionic contamination, and/or program disturb stresses. (The opposite effect of charge gain can occur when the floating gate slowly gains electrons with the control gate held at Vcc, thus causing an increase in threshold voltage.) As the threshold voltages of the memory cells decrease over time, it may result in a corresponding decrease in the read margin between states of the flash memory device. This phenomenon is referred to herein as “hot temperature stress” (HTS). With HTS, charges accumulated in the floating gate of a memory cell leak out of the floating gate to, for example, the substrate of the device. As the number of charges accumulated in the floating gate is reduced by this leakage, the threshold voltages of memory cells in respective states drop. The decrease in the threshold voltage (or charge-loss) due to HTS may increase as the amount of charges accumulated in the floating gate is increased. This charge-loss problem is not limited to devices having a floating gate structure. For example, memory devices with a charge trap structure may also suffer from such a charge-loss problem.
Charge-loss due to the above-described program/erase cycling and/or HTS effects causes variation in the threshold voltage distribution of each state. The varied threshold voltage distribution can be restored to an original threshold voltage distribution by the use of re-program (or refresh) operations.
Unfortunately, however, it may be difficult to restore charge-loss induced variations in a threshold voltage distribution by use of such re-program/refresh operations. For example, FIG. 2 illustrates target threshold voltage distributions for each state of a conventional memory device (dashed lines), along with the read voltages Read1, Read2 and Read 3 that define the boundaries between the four states. FIG. 2 also shows how the threshold voltage distribution may change due to, for example, HTS stress and/or cycling. In particular, the solid lines in FIG. 2 illustrate how the threshold voltage distributions may change due to a first amount of charge loss, while the dashed-dotted lines illustrate how the threshold voltage distributions may change due to a second, larger amount of charge loss. As illustrated in FIG. 2, if any memory cell of a programmed state has a threshold voltage lower than a read voltage that is used to determine the state of the memory cell, the memory cell is judged as an on-cell. This causes read error, and a memory block with such read error may be treated as a bad block. Such read errors may occur more frequently as the number of bits of data stored in each memory cell is increased. Furthermore, in a case where threshold voltage distributions of adjacent states are overlapped as illustrated by the threshold voltage distributions drawn using the dashed-dotted lines in FIG. 2, such a problem may become more serious.